An Overview
That chip scale package CSP, BGA is based on a further narrowing of the package size. CSP provides the bare chip and performance advantages with small flip chip die than the chip can be designed to grow the area or circumference of 1.2 to 1.5 times the package. And provides compatibility with the printed circuit board pad metallurgy of the solder ball and pin for reflow assembly process.
QFP and BGA CSP than shorter interconnect provides improved electrical and thermal performance, improved reliability, from 1997 has entered the initial stage of practical use, and will gradually become the high I / O pin count IC packages mainstream. In Japan mainly for ultra-high density and ultra-miniaturization of consumer electronics products, including memory cards, PC cards, handheld electronic devices, mobile phones and microcontrollers and other products; in the United States mainly for high-end electronic products in the field of the MCM, as a direct chip assembly KGD alternatives, as well as memory devices, especially I / O pin count of more than 2,000 high-performance electronic products.
Two processes and materials
CSP underfill process utilizes assembled under bump chip filled epoxy, shrinkage stress formed by light curing bumps and mechanical interconnection substrate pads (not welded). The overall thermal expansion characteristics of the assembly between the CSP underfill process can be reduced below the silicon substrate bonded thereto mismatch caused by the impact. Of conventional chip package, these stresses are absorbed by the lead normally natural flexibility. For direct attachment methods, such as solder ball array, the weakest point of the solder point within the structure itself, and therefore most vulnerable to stress failure. Underfill second role is to prevent moisture and other forms of pollution. Table 1 shows the assembly of the chip to the next CSP filler request. This material requires not only good performance, low cost, but also easy to repair.
Shanghai Chang Xiang Industrial Co., the world's top clients on the basis of practice, worked out a successful assembly CSP underfill process, filled with plastic expert Liu said: Many parameters can influence the outcome of underfill, although pollution is the most common cause of underfill defects but the following factors can not be ignored:
1, the surface tension of the solder resist layer,
2, the configuration of the solder resist layer (bypass hole, pin)
3, the surface energy of the chip passivation
4, I / O configuration (or surrounding area array arrangement) and spacing
5, the chip module / substrate gap size
6, the infusion of precision
7, the substrate temperature
8, the surface tension of the underfill material
9, the viscosity of the underfill material
10. The underfill material curing process
11, the bottom of the particle diameter of the filler
Three key problems and countermeasures
In the CSP underfill assembly process, the process must be effectively controlled, continuous and reliable results obtained, while maintaining the required level of production, the key issues include:
1 to obtain a complete and fill the bottom of the void-chip;
2, closely packed around the filler distribution of the chip;
3, to avoid contamination of other components;
4, the filling operation by means of a radio frequency (RF) shield housing or opening;
5, the control flux residues.
To ensure the CSP underfill assembly process quality, to choose suitable diameter needle mouth. For most applications, the 21st (inner diameter: 0.020in, outer diameter:.. 0.032in) or # 22 (inner diameter: 0.016in, outer diameter:.. 0.028in) the needle tip is the best choice of the bottom member is filled. The smaller diameter of the nozzle needle of liquid flow resistance is large, the result is the filling speed is slow, but it is sometimes necessary to use a small diameter needle through the tip rounded to reduce the size, to ensure that the filler material away from the other elements. In filling in, put the needle tip is close enough to the chip, and to avoid touching the back of the chip or contamination of the chip. Two chips sharing a fill area of a filling method may be employed, and the passive element will be parallel to the chip edge blocking effect. With a 90 degree angle to the chip edge position from the filler element will be an element to fill the opening to attract, resulting in voids underneath the CSP. With the increase in the underfill process using RF assembly, usually in the RF embodiment of the shield cover is assembled after the underfill process. Thus, product and process designers must work together to fill the bottom of the shield cover leave enough openings. Designers must also avoid the chips placed too close to the RF shielding cover, because the capillary action or high-speed filling may make the filling material flows within the RF shield on the cover or flip chip and CSP. Experience has shown that there is too much flux residues may have a negative impact on the filling process, this is because the filling material is attached to the flux residue, rather than adhering to the desired solder balls, chip and the substrate, resulting in empty, drag tail and other discontinuities. Thus, for example, by selective flux jetting technology, on the fluxing process control.
Four Reliability Test Results
For wafer level CSP (I / O count = 275) underfill / not filled assembled sample at a temperature range of 0 ~ 100 ℃, heating / cooling rate of 2 ~ 5 ℃ / min, the residence time of 10 to 20 minutes for environmental test. Sample wafer level CSP assembly at the bottom of unfilled 40 cycles to failure joints, and wafer-level CSP underfill assembled sample after 2000 cycles, not yet discovered solder joint failure. CSP assembly reliability decided to wafer level packaging type and the lowest value in ceramics and CTE equivalent absorption maximum value types, fill the bottom of the wafer level package assembly is necessary, it can also be used to enhance most other the reliability of the package assembly.
Five challenges facing
CSP underfill process of assembling a number of factors in the successful blending. CSP solder assembly process such as whether the physical package is damaged, lost or deformed, tidal influence, assembling PWB without deformation, the quality of the solder resist layer, micro-vias The quality of the fill material properties, residual stress and curing filling material drops accurate control of injection system for filling material volume infusion systems R & R and so on. Thus requiring product designers, manufacturing process engineers, craftsmen and fill material configuration drip system vendors and other co-operation and efforts, only to have achieved good performance, process controlled bottom CSP assembly filling process.
Six CSP assembly outlook
CSP reason for great concern, because it provides a higher packing density than the BGA, and flip chip than the use of low-density plate assembly. However, it is not like a flip chip assembly process is less complex, the flip chip does not deal with the problem of a bare chip, substantially in line with the SMT assembly process, and can be predicted and rework like as SMT. It is because of these advantages can not be compared, only to CSP to develop rapidly and entered the practical stage. There are a number of companies in Japan produce CSP, and now mobile phones, digital video recorders, notebook computers and other products increasingly used.
